1. Field of the Invention
The present invention relates to a program debugging system which writes in or modifies computer programs, and more particularly to a program debugging system which is applicable to computers with a stored-program arithmetic/logic controller capable of storing the whole program together with general data.
2. Description of the Prior Art
Recent advanced computer design technology has brought digital computers equipped with a stored-program arithmetic/logic controller. In such computers, when the need of program modification arises, the programmer rewrites the program using a program debugging system which detects errors made in the program rewriting operation and corrects these errors.
FIGS. 1, 2 and 3 show an example of the conventional program debugging system, which is provided in the plant controller "MELPLAC 550" (trade name) manufactured by Mitsubishi Electric Corp., and disclosed in its PP. MTPR instruction manual, p. 83-84.
FIG. 1 shows the arrangement of the above debugging system, in which a program debugging device 1 includes an interface 1a, a program debugging processor 1b, an error information read/edit unit 1c and a display controller 1d. A stored-program arithmetic/logic controller (will be termed simply "arithmetic/logic controller" hereinafter) 4 includes a central processing unit (CPU) 4a, a program memory 4b, a data memory 4c, an input/output interface 4d, an interface 4e, an error detector 4f, an error information register 4g and an error information memory 4h. A keyboard 2 as an operator console is connected to the program debugging device 1, and it has keys for issuing debugging process commands to the program debugging processor 1b and error information readout commands to the error information read/edit unit 1c. A display unit 3 is connected to the output of the display controller 1d.
The interface 1a is connected with the error information read/edit unit 1c and program debugging processor 1b, and also connected with the interface 4e of the arithmetic/logic controller 4 for implementing data transaction between the arithmetic/logic controller 4 and program debugging device 1.
The program debugging processor 1b is activated in response to the debugging process command issued on the keyboard 2, and it operates to convert the debugging process command to the signal to be fed to the arithmetic/ logic controller 4, write a user program into the program memory 4b, and debug the user program during a rewriting operation.
The error information read/edit unit 1c is activated in response to the error information read command from the keyboard 2, and it operates to read out the error information memory 4h and edit the contents. The display controller 1d operates to supply error information edited by the error information read/edit unit 1c.
The CPU 4a implements arithmetic and logic operations and comparison operations for data in accordance with the user program stored in the program memory 4b. The program memory 4b stores the control program as well as user programs. The data memory 4c stores various data processed by the CPU 4a under control of the CPU 4a. The data memory 4c is also capable of temporarily holding the data related to the error in the suitable area for the purpose of analysis of an error which has occurred in the arithmetic/logic controller 4. So as to execute such function, it is necessary to register user programs processing the error related data as an error interrupt routine started at the time of error occurrence to be saved in the data memory 4c.
The error detector 4f detects errors such as overflow of operational result during the execution of operation for data by the CPU 4a, and indicates the occurrence of error to the error information register 4g. The error information register 4g receives the error message from the error detector 4f and stores error information necessary for the error analysis, such as the error code and program address at which the error has occurred, in the error information memory 4h. The error information memory 4h stores error information fed by the error information register 4g.
The input/output interface 4d is to transfer various data between the arithmetic/logic controller 4 and the control object process (not shown). The interface 4e is connected with the interface 1a for implementing data transaction between the arithmetic/logic controller 4 and the program debugging device 1.
The operation of the foregoing program debugging system is as follows. When power is turned on by the operator, the arithmetic/logic controller 4 starts operating as shown in FIG. 2(a). The CPU 4a reads out the program sequentially from the program memory 4b, reads out data from the data memory 4c in accordance with the program, stores data produced as a result of operation in the data memory 4c, reads external data from the control object process (not shown) via the input/output interface 4d, and stores the external data in the data memory 4c. During the execution of the above processes, if the occurrence of error such as overflow of operational result is detected by the error detector 4f and indicated to the error information register 4g, the error code and program address pertinent to that error are recorded by the error information register 4g into the error information memory 4h. At the same time, the occurrence of error is informed to the operator by means of an error indicator lamp (not shown) provided on the arithmetic/logic controller 4. When the operator activates the keys on the keyboard 2 to issue the debugging process command signal, the program debugging processor 1b starts operating as shown in FIG. 2(b). Upon reception of the debugging process command signal by the program debugging processor 1b and delivery in the form of the input signal to the arithmetic/logic controller 4, a debugging process specified by the debugging process command signal, such as correction of error in the user program in the program memory or rewriting of data in the data memory 4c, will take place. Alternatively, when the operator activates the keys on the keyboard 2 to issue the error information read command signal, the error information read/edit unit 1c starts operating. Error information is read out of the error information memory 4h and edited by the error information read/edit unit 1c, and displayed under control of the display controller 1d on the display unit 3 as shown in FIG. 3.
The conventional program debugging system arranged as described above has the following deficiencies. Error detection for such as overflow of operational result occurring in the arithmetic/logic controller 4 is implemented by the error detector 4f as mentioned above, and in this case of the error detecting operation the error detector 4f interrupts the operation of the CPU 4a. Error related data mentioned above at the occurrence of error is indispensable for the debugging process by the program debugging device 1, and it must be held for allowing access by the program debugging device 1. For this purpose of holding error related data, it has been attempted to prepare an error interrupt routine as shown in FIG. 2(b) in the program memory 4b so that the data is saved in a certain area of the data memory 4c and the saved data is retrieved and displayed by the program debugging device 1 on the display unit 3 at the time of error analysis. Because the contents stored automatically in the error information memory 4h merely include the error code and program address at the occurrence of error, and do not include data itself which is conceivably the cause of the error. Recording of detailed data inclusive of data which has directly caused the error in the data memory 4c requires a complex program. Change of address of error related data to be stored in the data memory 4c requires the modification of the error interrupt processing routine, which necessitates rewriting of the error interrupt processing routine in the program memory 4b by suspending the operation of the CPU 4a.